1. Field of the Invention
The invention relates to a system and a method for estimating power consumption of a semiconductor chip design, and more particularly to a system and method for estimating power consumption of a semiconductor chip design described at the register-transfer level and using arc-based power models.
2. Description of the Related Art
The advent of wireless and mobile technologies increases the demand for low power integrated circuit designs, particularly for use in battery-powered applications. Because the architectural choices for an integrated circuit (or chip) design often determines it power characteristics, it is becoming imperative to access the power dissipation level of a chip design at an early stage in the design cycle where significant design changes can still be made to optimize the power characteristics.
In a typical design process of an integrated circuit, the chip design, defined by a functional specification and an interface description, is created using a computed aided design tool and expressed at the register-transfer level (RTL) using a hardware description language (HDL), such as Verilog. HDL describes the chip design in behavior terms and does not include detailed structural description of the design. When the designer is satisfied with the design at the register-transfer level, the RTL chip design is then synthesized to transform the behavior description into a circuit level or a gate level description. The circuit level or gate level description can be further optimized and verified before the design is transformed into a mask set for manufacturing the integrated circuit.
In a typical design process, computer-aided design (CAD) tools are generally used to simulate the design defined at RTL to ensure that the design meets the functional and timing requirements of the design. The simulation result may include information that can be used for extracting activity and duty cycle data for the internal nodes of the design. It is also desirable to perform RTL power analysis to access the power consumption level of the design so that optimization can be made to ensure that the final design implementation will meet the power requirements. However, conventional power analysis tools typically analyze a design at the circuit or gate level, thus requiring a designer to make final design choices and fully synthesized the design in order to estimate power. Because design synthesis is a time consuming process, it is often inconvenient and burdensome for a designer to synthesize a design early on in the design cycle in order to access the power consumption level. Also, gate-level power analysis is less useful because, in a design cycle, the design is often modified and the power characteristics need to be reassessed repeatedly.
U.S. Pat. No. 6,151,568 issued to Allen et al., entitled “Power Estimation Software System” (hereinafter “the '568 patent”), describes a method for analyzing the power consumption of an electrical design specified at the register-transfer level (RTL). The power estimation system of the '568 patent predicts the power consumption of a design using information about the switching activity of the design and a power model library. As power dissipation is necessarily a property of structural elements, RTL power analysis generally requires a transformation of an RTL HDL model into a fully structural model that is taken as an approximation of the final design implementation. The '568 patent describes one exemplary method for accomplishing the RTL-to-structural model transformation whereby micro-architectural inferencing is used to generate a netlist composed of macro instances. The '568 patent then proceeds to estimate power dissipation of the structural macro instances based on switching activities and duty cycles of the signals at the periphery of the macro instances.
Generally, a power model of a cell (or a gate) contains one of more descriptions of power dissipating conditions associated with the cell. Two types of cell power models have found widespread use—pin-based and arc-based. Pin-based models describe power dissipation of a cell based on single transitions on one of the cell's pins, possibly under specific Boolean conditions describing the states of the other pins. The pin-based models are easy to evaluate using switching activity and duty cycle data associated with the pins. The evaluation of the power model involves simply using the activity values (that is, the switching activity or the duty cycle) of each pin. However, power estimation based on pin-based power models is known to be less accurate than arc-based power models.
Arc-based power models describe power dissipation of a cell based on a sequence of events (or logical transitions) on the cell's pins. The sequence of events is usually a transition on an input pin followed by a transition on an output pin, called an arc. Hence, the power model is “arc” based. More complicated arc-based power models may reference a sequence of more than two transitions, or include a Boolean condition describing logical states on the cell's pins during this sequence. If a gate-level netlist for a design is available, the arc-based models can be evaluated for power consumption by counting the number of times the specified sequences of transitions (corresponding to the arcs of the cell) actually happened during the period of analysis. It is possible to carry out such an evaluation because the gate-level netlist provides a direct mapping of the instances of the power models to the arc descriptions. However, for RTL power analysis, evaluation of arc-based power models poses a significant challenge because information about the sequence of transitions on the pins cannot be directly derived from activities on the pins of the structural blocks.
Another difficulty of using arc-based power models for RTL power analysis stems from the large variance of syntax used to describe the arcs. Not only are there multiple library formats used by different CAD vendors to describe the power arcs (for example, Advanced Library Format (ALF), Open Library API (OLA), and Synopsys' .lib formats), there could be multiple ways to represent the same arc even within one library format. For example, the ALF format allows the following expressions to be used to describe an input-to-output arc of a 2-input NAND gate having the function Y=!(A && B):                (01A-> 10Y)        (01A-> 10Y && B)        (01A && B)        (10Y && B)where the symbol “->” denotes a sequence of events, the second event following the first event; and the symbol “&&” denotes a Boolean “AND” condition. A description of the ALF format can be found in Advanced Library Format for ASIC Technology, Cells, & Blocks Version 2.0 available from the EDA Industry Working Groups website (www.eda.org/alf/homepage/alf—2.0.pdf). Other library formats allow similar variance in the power arc descriptions. Thus, for a power analysis tool to support arc-based power models, the tool needs to be able to handle power arc descriptions written in all different library formats and all different variance within the library formats.        
Because arc-based power models provide more accurate power estimation, it is desirable to perform RTL power analysis using arc-based power models so that accurate power estimation can be obtained early on in the chip design cycle.